Search - lattice verilog

[Other resource] 9.8_DISP256_GUO

Description: 基于Verilog-HDL的硬件电路的实现 9.8 基于256点阵的汉字显示　　9.8.1 单个静止汉字显示的设计原理及其仿真实现　　9.8.2 单个静止汉字显示的硬件实现　　9.8.3 多个静止汉字显示的设计原理及其硬件实现　　9.8.4 单个运动汉字显示的设计原理及其硬件实现　　9.8.5 多个运动汉字显示的设计原理及其硬件实现 -based on Verilog-HDL hardware Circuit of 9.8 based on the lattice of 256 Chinese character display 9.8.1 static single Chinese character display and the design principle Simulation 9.8.2 single Chinese character was geostationary said the number of hardware 9.8.3 static display Chinese characters and hardware design principle to achieve single-9.8.4 - Movement of the Chinese character display and hardware design principle to achieve a number of campaigns 9.8.5 Chinese character display and the design principle Hardware Implementation
Platform: | Size: 1198 | Author: 宁宁 | Hits:

[Other resource] uart_core_vhdlORverilog

Description: 串uart的vhdl，verilog，lattic实现原码里面有四个文件,分别UART 源码 (lattice version)\\uart 源码 (Verilog)\\uart 源码 (VHDL)\\uart16550.tar-uart series of vhdl and verilog. lattic achieve the original code, there are four documents, Source respectively UART (lattice version) \\ uart source (Verilog) \\ uart source (VHDL) \\ uart16550.tar
Platform: | Size: 295101 | Author: efly | Hits:

[Other resource] Lattice_Verilog

Description: 本文讨论了AR模型及线性预测的原理，在浮点型DSP TMS320C6713B上实现了语音信号线性预测系数(LPC)的提取，并利用LPC系数用Verilog语言实现了AR模型的Lattice结构。
Platform: | Size: 14313 | Author: 万金油 | Hits:

[VHDL-FPGA-Verilog] pcit32_verilog_lattice

Description: 这个我也太清楚是什么反正师兄们说有用发大家-I am also very clear that what is useful anyway, say senior U.S. fa
Platform: | Size: 430080 | Author: wang | Hits:

[VHDL-FPGA-Verilog] uart16450

Description: uart 16450合集,xilin altera lattice-collection of uart controller 16450
Platform: | Size: 822272 | Author: jhv | Hits:

[VHDL-FPGA-Verilog] I2C_xo

Description: IIC的verilog源码，可以在Lattice的XO DEMO板上运行的IIC代码。内附说明文件-IIC' s verilog source code, you can Lattice' s XO DEMO board to run IIC code. Included documentation
Platform: | Size: 6568960 | Author: 高小高 | Hits:

[VHDL-FPGA-Verilog] UART_VHDL_Verilog_Lattice

Description: 本压缩包中含有串口程序的VHDL,Verilog，Lattice三种版本的代码，均已实现。在压缩包中，含有非常详细的串口的实现规格。各种版本的代码中，含有完成的源文件，测试文件，模拟文件。-This compressed package contains serial process VHDL, Verilog, Lattice three versions of the code, have been achieved. In the compressed package, contains very detailed specifications of the serial implementation. Various versions of the code, containing the complete source files, test files, simulation files.
Platform: | Size: 293888 | Author: shishu | Hits:

[Software Engineering] Advanced_Verilog_Design

Description: 以Lattice 器伴为例,描述如何在Verilog中指定管脚属饪功能(OE,RESET,IO CELL寄存器,双向IO,Latch IO,管脚Pin number, synthesis属性,输出电气规格...),状态机的使用,及其它Verilog进阶功能-With Lattice devices for example, it describes how to specify the pin function in Verilog (OE, RESET, IO CELL register, bi-directional IO, Latch IO, assign Pin number, synthesis properties, the output electrical specifications ...), using State Machine, and other advanced features of Verilog.
Platform: | Size: 126976 | Author: Tim | Hits:

[VHDL-FPGA-Verilog] LED_FINAL2

Description: 用Verilog HDL 实现16*32LED点阵的静态显示-Using Verilog HDL to achieve 16* 32LED lattice static display
Platform: | Size: 2048 | Author: 张微 | Hits:

[VHDL-FPGA-Verilog] FPGA_UART

Description: 用Verilog语言实现的FPGA UART独立收发模块思路简单，代码简洁。在Lattice LFE3EA VERSA开发板上验证通过,编译器Lattice Diamond. 功能：串口收到数据后立即回传，此后每一秒串口数据+1再发送。-Using Verilog language independent of FPGA UART transceiver idea is simple, concise code. Development board in Lattice LFE3EA VERSA verified by the compiler Lattice Diamond. Features: Serial data is received immediately after the return, then every second serial port and then send the data+ 1.
Platform: | Size: 3072 | Author: 朱强光 | Hits:

[VHDL-FPGA-Verilog] ddr2_demo

Description: lattice 操作DDR2控制器verilog源代码-the verilog source code of ddr2 control of lattice
Platform: | Size: 886784 | Author: 肖涛 | Hits:

[VHDL-FPGA-Verilog] Verilog_lattice-fpga

Description: Verilog教程lattice FPGA-Verilog tutorial Lattice FPGA
Platform: | Size: 143360 | Author: qiumh | Hits:

[Other] NandController(lattice)

Description: NAND Flash控制器源码 Verilog-NAND Flash controller source Verilog
Platform: | Size: 584704 | Author: wang | Hits:

[VHDL-FPGA-Verilog] ddr_top

Description: This VHDL or Verilog source code is intended as a design reference // which illustrates how these types of functions can be implemented. // It is the user s responsibility to verify their design for // consistency and functionality through the use of formal // verification methods. Lattice Semiconductor provides no warranty // regarding the use or functionality of this code.- This VHDL or Verilog source code is intended as a design reference // which illustrates how these types of functions can be implemented. // It is the user s responsibility to verify their design for // consistency and functionality through the use of formal // verification methods. Lattice Semiconductor provides no warranty // regarding the use or functionality of this code.
Platform: | Size: 2048 | Author: LJ | Hits:

[VHDL-FPGA-Verilog] ddr_sig

Description: This VHDL or Verilog source code is intended as a design reference // which illustrates how these types of functions can be implemented. // It is the user s responsibility to verify their design for // consistency and functionality through the use of formal // verification methods. Lattice Semiconductor provides no warranty // regarding the use or functionality of this code.- This VHDL or Verilog source code is intended as a design reference // which illustrates how these types of functions can be implemented. // It is the user s responsibility to verify their design for // consistency and functionality through the use of formal // verification methods. Lattice Semiconductor provides no warranty // regarding the use or functionality of this code.
Platform: | Size: 2048 | Author: LJ | Hits:

[Other] verilog

Description: 用verilog语言编写的点阵的应用，显示一个桃形的图样-Lattice using verilog language applications, showing a pattern Peach
Platform: | Size: 1024 | Author: 廖锦程 | Hits:

[Other] SensorHubDesignFilesSourceCode

Description: sensor-hub技术是最新出来的技术，目前用在智能手机领域，手机里面的传感器越来越多，这给CPU带来很大的负担，功耗也随之提高。sensor-hub技术出来后，可以有效的解决这个问题，这是运行在lattice FPGA平台上的verilog源代码，欢迎大家一起交流学习，希望能给你带来帮助。-Sensor- the hub is the latest technology, the current use in the field of smart phones, mobile phone inside the sensor is increasing, which bring great burden to the CPU, power consumption increases.Sensor- the hub technology comes out, can effectively solve the problem, it is running on the lattice verilog code on FPGA platform, welcome to learn together, hope I can bring you help.
Platform: | Size: 9956352 | Author: 叶胜东 | Hits:

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